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Precoder/two-stage equaliser for block-based single-carrier transmission with insufficient guard interval

dc.citation.epage747en_US
dc.citation.issue13en_US
dc.citation.spage746en_US
dc.citation.volume47en_US
dc.citation.woscount1
dc.contributor.authorSong, Y.en_US
dc.contributor.authorFung, C. C.en_US
dc.contributor.authorWong, K. T.en_US
dc.contributor.authorMeng, H.en_US
dc.contributor.authorTseng, D. -F.en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:31:51Z
dc.date.available2014-12-08T15:31:51Z
dc.date.issued2011-06-23en_US
dc.description.abstractProposed is a zero-inserting precoder and a two-stage linear equaliser, to shorten the guard interval in block-based single-carrier modulation. The first-stage equaliser consists of a linear single-tapper-subcarrier frequency-domain equaliser. The second-stage equaliser maximises the SINR, in the time-domain, based on the interference-plus-noise estimated from the zero-padded sub-intervals of the single-carrier modulation. This proposed scheme is applicable even without cyclic prefixing.en_US
dc.identifier.doi10.1049/el.2011.0559en_US
dc.identifier.issn0013-5194en_US
dc.identifier.journalELECTRONICS LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1049/el.2011.0559en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/22497
dc.identifier.wosnumberWOS:000291928100012
dc.language.isoen_USen_US
dc.titlePrecoder/two-stage equaliser for block-based single-carrier transmission with insufficient guard intervalen_US
dc.typeArticleen_US

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