Dual-mode Viterbi decoder design for cellular mobile
| dc.citation.epage | 1033 | en_US |
| dc.citation.spage | 1029 | en_US |
| dc.contributor.author | Chen, AY | en_US |
| dc.contributor.author | Wu, CY | en_US |
| dc.contributor.author | Wen, KA | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:27:39Z | |
| dc.date.available | 2014-12-08T15:27:39Z | |
| dc.date.issued | 1996 | en_US |
| dc.description.abstract | The Viterbi algorithm is widely applied for communication to derive the maximun-likehood sequence estimates of transmitted data on channels with intersymbol interference (ISI) and/or coding. In this paper, we provide a VLSI design of Viterbi decoder for IS-54. Design features includes: switchable (2,1,5),(4,1,5) coder design, data inter-leaving, soft - decision. For hardware constrain, area efficiency is of great concern in handset design. Hence, optimized area efficient design is imple-mented. | en_US |
| dc.identifier.isbn | 0-7803-3692-5 | en_US |
| dc.identifier.journal | PIMRC'96 - THE SEVENTH IEEE INTERNATIONAL SYMPOSIUM ON PERSONAL, INDOOR AND MOBILE RADIO COMMUNICATIONS, PROCEEDINGS, VOLS 1-3 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/19917 | |
| dc.identifier.wosnumber | WOS:A1996BH25X00213 | |
| dc.language.iso | en_US | en_US |
| dc.title | Dual-mode Viterbi decoder design for cellular mobile | en_US |
| dc.type | Proceedings Paper | en_US |
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