ANALYSIS OF SURFACE-STATE EFFECT ON GATE LAG PHENOMENA IN GAAS-MESFETS
| dc.citation.epage | 1512 | en_US |
| dc.citation.issue | 9 | en_US |
| dc.citation.spage | 1504 | en_US |
| dc.citation.volume | 41 | en_US |
| dc.citation.woscount | 47 | |
| dc.contributor.author | LO, SH | en_US |
| dc.contributor.author | LEE, CP | en_US |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:03:47Z | |
| dc.date.available | 2014-12-08T15:03:47Z | |
| dc.date.issued | 1994-09-01 | en_US |
| dc.description.abstract | A two-dimensional transient simulation of the gate lag phenomenon in GaAs MESFET's has been performed. Our results show that the charge exchanges in the population of the surface states at the ungated access region of FET's are responsible for this slow transient phenomenon. The measured ''hole-trap-like'' DLTS signal is directly related to the re-emission of the holes, trapped during the filling pulse. Higher gate pulse can cause more serious lag phenomenon due to larger modulation of surface charge density. Devices with shorter N+-gate spacing and lower surface state densities are shown to have less gate lag effect. | en_US |
| dc.identifier.doi | 10.1109/16.310100 | en_US |
| dc.identifier.issn | 0018-9383 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/16.310100 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/2332 | |
| dc.identifier.wosnumber | WOS:A1994PE02600003 | |
| dc.language.iso | en_US | en_US |
| dc.title | ANALYSIS OF SURFACE-STATE EFFECT ON GATE LAG PHENOMENA IN GAAS-MESFETS | en_US |
| dc.type | Article | en_US |