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Impacts of a polycrystalline-silicon buffer layer on the performance and reliability of strained n-channel metal-oxide-semiconductor field-effect transistors with SiN capping

dc.citation.epageen_US
dc.citation.issue12en_US
dc.citation.volume90en_US
dc.citation.woscount6
dc.contributor.authorLu, Ching-Senen_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHuang, Jian-Mingen_US
dc.contributor.authorLee, Yao-Jenen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:14:29Z
dc.date.available2014-12-08T15:14:29Z
dc.date.issued2007-03-19en_US
dc.description.abstractCharacteristics of n-channel metal-oxide-semiconductor field-effect transistors with SiN capping were investigated in this work. Although the SiN capping could dramatically enhance the carrier mobility and thus the device drive current, the resistance to hot-carrier degradation is compromised as well, owing to the large amount of hydrogen contained in the SiN layer which may diffuse into the channel region during the process. To eliminate this shortcoming, the insertion of an ultrathin (10 nm) polycrystalline-silicon buffer layer between the gate and the SiN capping was proposed and demonstrated to restore the hot-carrier reliability of the devices without compromising the current enhancement due to the SiN capping. (c) 2007 American Institute of Physics.en_US
dc.identifier.doi10.1063/1.2715122en_US
dc.identifier.issn0003-6951en_US
dc.identifier.journalAPPLIED PHYSICS LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1063/1.2715122en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/11020
dc.identifier.wosnumberWOS:000245135800068
dc.language.isoen_USen_US
dc.titleImpacts of a polycrystalline-silicon buffer layer on the performance and reliability of strained n-channel metal-oxide-semiconductor field-effect transistors with SiN cappingen_US
dc.typeArticleen_US

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