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Scheduling of multiple in-line steppers for semiconductor wafer fabs

dc.citation.epage398en_US
dc.citation.issue3en_US
dc.citation.spage384en_US
dc.citation.volume45en_US
dc.citation.woscount1
dc.contributor.authorChiou, Chie-Wunen_US
dc.contributor.authorWu, Muh-Cherngen_US
dc.contributor.department工業工程與管理學系zh_TW
dc.contributor.departmentDepartment of Industrial Engineering and Managementen_US
dc.date.accessioned2014-12-08T15:36:09Z
dc.date.available2014-12-08T15:36:09Z
dc.date.issued2014-03-01en_US
dc.description.abstractA few prior studies noticed that an in-line stepper (a bottleneck machine in a semiconductor fab) may have a capacity loss while operated in a low-yield scenario. To alleviate such a capacity loss, some meta-heuristic algorithms for scheduling a single in-line stepper were proposed. Yet, in practice, there are multiple in-line steppers to be scheduled in a fab. This article aims to enhance prior algorithms so as to deal with the scheduling for multiple in-line steppers. Compared to prior studies, this research has to additionally consider how to appropriately allocate jobs to various machines. We enhance prior algorithms by developing a chromosome-decoding scheme which can yield a job-allocation decision for any given chromosome (or job sequence). Seven enhanced versions of meta-heuristic algorithms (genetic algorithm, Tabu, GA-Tabu, simulated annealing, M-MMAX, PACO and particle swarm optimisation) were then proposed and tested. Numerical experiments indicate that the GA-Tabu method outperforms the others. In addition, the lower the process yield, the better is the performance of the GA-Tabu algorithm.en_US
dc.identifier.doi10.1080/00207721.2012.724093en_US
dc.identifier.issn0020-7721en_US
dc.identifier.journalINTERNATIONAL JOURNAL OF SYSTEMS SCIENCEen_US
dc.identifier.urihttp://dx.doi.org/10.1080/00207721.2012.724093en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/24505
dc.identifier.wosnumberWOS:000335668300010
dc.language.isoen_USen_US
dc.subjectschedulingen_US
dc.subjectsemiconductoren_US
dc.subjectflow shopen_US
dc.subjectport capacity constraintsen_US
dc.subjectgenetic algorithmen_US
dc.subjectmeta-heuristic algorithmsen_US
dc.titleScheduling of multiple in-line steppers for semiconductor wafer fabsen_US
dc.typeArticleen_US

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