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A novel 25-nm modified Schottky-barrier FinFET with high performance

dc.citation.epage432en_US
dc.citation.issue6en_US
dc.citation.spage430en_US
dc.citation.volume25en_US
dc.citation.woscount36
dc.contributor.authorTsui, BYen_US
dc.contributor.authorLin, CPen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:39:05Z
dc.date.available2014-12-08T15:39:05Z
dc.date.issued2004-06-01en_US
dc.description.abstractHigh-performance modified Schottky barrier (MSB) FinFET with 25-nm channel length and fully silicided source/drain (S/D) is proposed for the first time. Using an implant-to-silicide technique, an ultrashort and defect-free S/D extension can be formed at temperature as low as 600 degreesC. The MSB FinFET exhibits better current-voltage characteristics than those of published Schottky barrier devices and FinFETs. With 4-nm-thick gate oxide, the I-on /I-off current ratio higher than 10(9) is achieved. The subthreshold swing of 25-nm and 49-nm MSB FinFETs is 83 and 64.5 mV/dec at room temperature. The advantage of low thermal budget relaxes the thermal stability issue for metal gate/high-kappa dielectric integration. It is believed that the proposed MSB FinFET would be a very promising nano device.en_US
dc.identifier.doi10.1109/LED.2004.828980en_US
dc.identifier.issn0741-3106en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2004.828980en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/26722
dc.identifier.wosnumberWOS:000221659700029
dc.language.isoen_USen_US
dc.subjectFinFETen_US
dc.subjectSchottky barrieren_US
dc.subjectsilicon-on-insulator (SOI)en_US
dc.titleA novel 25-nm modified Schottky-barrier FinFET with high performanceen_US
dc.typeArticleen_US

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