A new DLL-based approach for all-digital multiphase clock generation
| dc.citation.epage | 475 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 469 | en_US |
| dc.citation.volume | 39 | en_US |
| dc.citation.woscount | 34 | |
| dc.contributor.author | Chung, CC | en_US |
| dc.contributor.author | Lee, CY | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:39:31Z | |
| dc.date.available | 2014-12-08T15:39:31Z | |
| dc.date.issued | 2004-03-01 | en_US |
| dc.description.abstract | A new DLL-based approach for all-digital multiphase clock generation is presented. By-using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-based solution can overcome the false-lock problem in conventional designs. Furthermore, the proposed all-digital multiphase clock generator (ADMCG) can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity in many different applications. The test chip shows that our proposal demonstrates a wide frequency range to meet the needs of many digital. communication applications. | en_US |
| dc.identifier.doi | 10.1109/JSSC.2003.822890 | en_US |
| dc.identifier.issn | 0018-9200 | en_US |
| dc.identifier.journal | IEEE JOURNAL OF SOLID-STATE CIRCUITS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/JSSC.2003.822890 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/26981 | |
| dc.identifier.wosnumber | WOS:000220018900008 | |
| dc.language.iso | en_US | en_US |
| dc.subject | delay-locked loops (DLLs) | en_US |
| dc.subject | digitally controlled delay line (DCDL) | en_US |
| dc.subject | multiphase clock generation | en_US |
| dc.subject | phase synchronization | en_US |
| dc.title | A new DLL-based approach for all-digital multiphase clock generation | en_US |
| dc.type | Article | en_US |