EFFECT OF BACK-GATE BIAS ON TUNNELING LEAKAGE IN A GATED P+-N DIODE
| dc.citation.epage | 251 | en_US |
| dc.citation.issue | 5 | en_US |
| dc.citation.spage | 249 | en_US |
| dc.citation.volume | 12 | en_US |
| dc.citation.woscount | 6 | |
| dc.contributor.author | CHEN, MJ | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:05:16Z | |
| dc.date.available | 2014-12-08T15:05:16Z | |
| dc.date.issued | 1991-05-01 | en_US |
| dc.description.abstract | On a thin-oxide gate-controlled p+-n diode, this work first exhibits experimentally not only the substrate-bias-dependent characteristics of the tunneling leakage current but also the tunneling leakage characteristics independent of the substrate bias. This observation can be reasonably explained by the nature of the modulation of the surface space-charge region over the heavily doped p+ region as well as over the n-type substrate. Based on this work, the original understanding of such tunneling leakage has been improved. | en_US |
| dc.identifier.issn | 0741-3106 | en_US |
| dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/3804 | |
| dc.identifier.wosnumber | WOS:A1991FJ40000020 | |
| dc.language.iso | en_US | en_US |
| dc.title | EFFECT OF BACK-GATE BIAS ON TUNNELING LEAKAGE IN A GATED P+-N DIODE | en_US |
| dc.type | Article | en_US |