New RSA cryptosystem hardware design based on Montgomery's algorithm
| dc.citation.epage | 913 | en_US |
| dc.citation.issue | 7 | en_US |
| dc.citation.spage | 908 | en_US |
| dc.citation.volume | 45 | en_US |
| dc.citation.woscount | 38 | |
| dc.contributor.author | Yang, CC | en_US |
| dc.contributor.author | Chang, TS | en_US |
| dc.contributor.author | Jen, CW | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:48:54Z | |
| dc.date.available | 2014-12-08T15:48:54Z | |
| dc.date.issued | 1998-07-01 | en_US |
| dc.description.abstract | In this paper, we propose a new algorithm based on Montgomery's algorithm to calculate modular multiplication that is the core arithmetic operation in an RSA cryptosystem. The modified algorithm eliminates over-large residue and has very short critical path delay that yields a very high-speed processing. The nevi architecture based on this modified algorithm takes about 1.5n(2) clock cycles on the average to finish one n-bit RSA operation. We have implemented a 512-bit single-chip RSA processor based on the modified algorithm with Compass 0.6-mu m SPDM CMOS cell library. The simulation results show that the processor can operate up to 125 MHz and deliver the baud rate of 164 Kbits/s on the average. | en_US |
| dc.identifier.doi | 10.1109/82.700944 | en_US |
| dc.identifier.issn | 1057-7130 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/82.700944 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/32521 | |
| dc.identifier.wosnumber | WOS:000074747400020 | |
| dc.language.iso | en_US | en_US |
| dc.title | New RSA cryptosystem hardware design based on Montgomery's algorithm | en_US |
| dc.type | Article | en_US |