Drain/gate-voltage-dependent on-current and off-current instabilities in polycrystalline silicon thin-film transistors under electrical stress

Abstract

The On-current (I(on)) and Off-current (I(off)) instabilities of polycrystalline silicon thin-film transistors (poly-Si TFTs) were investigated under various stress conditions. The stress-induced device degradation was studied by measuring the dependences Of I(on) and I(off) on the drain/gate voltages. From the results, dissimilar variations in I(on) and I(off) were observed. The differences can be attributed to the variances in the amount of trap charges in the gate oxide and the spatial distributions of the trap states generated in the poly-Si channel. A comprehensive model for the degradation Of I(on) and I(off) in poly-Si TFTs under various electrical stress conditions was suggested.