Leakage behavior of the quasi-superlattice stack for multilevel charge storage
| dc.citation.epage | 3689 | en_US |
| dc.citation.issue | 18 | en_US |
| dc.citation.spage | 3687 | en_US |
| dc.citation.volume | 84 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Chang, TC | en_US |
| dc.contributor.author | Yan, ST | en_US |
| dc.contributor.author | Liu, PT | en_US |
| dc.contributor.author | Chen, CW | en_US |
| dc.contributor.author | Wu, HH | en_US |
| dc.contributor.author | Sze, SM | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:39:12Z | |
| dc.date.available | 2014-12-08T15:39:12Z | |
| dc.date.issued | 2004-05-03 | en_US |
| dc.description.abstract | The leakage behavior of the quasi-superlattice structure has been characterized by current-voltage measurements at room temperature and 50 K. A resonant tunnelinglike leakage characteristic is observed at low temperature. The resonant tunneling occurs at around 2, 5.2, and 7 V under a gate voltage swept from 0 to 10 V. A concise physical model is proposed to characterize the leakage mechanism of tunneling for the quasi-lattice structure and suggests that the considerations of the operating voltage for the two-bit per cell nonvolatile-memory device need to be taken into account. (C) 2004 American Institute of Physics. | en_US |
| dc.identifier.doi | 10.1063/1.1739514 | en_US |
| dc.identifier.issn | 0003-6951 | en_US |
| dc.identifier.journal | APPLIED PHYSICS LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1063/1.1739514 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/26788 | |
| dc.identifier.wosnumber | WOS:000221062500085 | |
| dc.language.iso | en_US | en_US |
| dc.title | Leakage behavior of the quasi-superlattice stack for multilevel charge storage | en_US |
| dc.type | Article | en_US |