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FAULT ANALYSIS ON (K+1)-VALUED PLA STRUCTURE LOGIC-CIRCUITS

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dc.citation.epage1010en_US
dc.citation.issue6en_US
dc.citation.spage1001en_US
dc.citation.volumeE76Aen_US
dc.citation.woscount0
dc.contributor.authorWANG, HMen_US
dc.contributor.authorLEE, CLen_US
dc.contributor.authorCHEN, JEen_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.date.accessioned2014-12-08T15:04:30Z
dc.date.available2014-12-08T15:04:30Z
dc.date.issued1993-06-01en_US
dc.description.abstractThis paper presents a general form and a set of basic gates to implement (K+1)-valued PLA structure logic circuits. A complete fault analysis on the proposed circuit has been done and it is shown that all fanout stem faults can be collapsed to branch faults. A procedure for fault collapsing is derived. For any function implemented in the (K+1)-valued circuit, the number of remaining faults is smaller than that of the 2-valued circuit after the collapsing, where the value of K is dependent on the number of outputs and the assignment of the OR plane of the 2-valued logic circuit.en_US
dc.identifier.issn0916-8508en_US
dc.identifier.journalIEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCESen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/2984
dc.identifier.wosnumberWOS:A1993LK30000022
dc.language.isoen_USen_US
dc.subjectFAULT ANALYSIS, (K+1)-VALUED LOGIC CIRCUITSen_US
dc.subjectPLAen_US
dc.subject2-LEVELen_US
dc.subjectCIRCUITen_US
dc.titleFAULT ANALYSIS ON (K+1)-VALUED PLA STRUCTURE LOGIC-CIRCUITSen_US
dc.typeArticleen_US

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