Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack
| dc.citation.epage | 38 | en_US |
| dc.citation.issue | en_US | |
| dc.citation.spage | 35 | en_US |
| dc.citation.volume | 109 | en_US |
| dc.citation.woscount | 4 | |
| dc.contributor.author | Cheng, C. H. | en_US |
| dc.contributor.author | Chou, K. I. | en_US |
| dc.contributor.author | Chin, A. | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:31:00Z | |
| dc.date.available | 2014-12-08T15:31:00Z | |
| dc.date.issued | 2013-09-01 | en_US |
| dc.description.abstract | We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (V-t) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process. (C) 2013 Elsevier B.V. All rights reserved. | en_US |
| dc.identifier.doi | 10.1016/j.mee.2013.03.082 | en_US |
| dc.identifier.issn | 0167-9317 | en_US |
| dc.identifier.journal | MICROELECTRONIC ENGINEERING | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1016/j.mee.2013.03.082 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/22106 | |
| dc.identifier.wosnumber | WOS:000321229200011 | |
| dc.language.iso | en_US | en_US |
| dc.subject | TiLaO | en_US |
| dc.subject | La2O3 | en_US |
| dc.subject | Gate first | en_US |
| dc.subject | Low EOT | en_US |
| dc.title | Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack | en_US |
| dc.type | Article | en_US |