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An Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processors

dc.citation.epage2910en_US
dc.citation.spage2901en_US
dc.citation.volumeE100Aen_US
dc.contributor.authorLiao, Chien-Huien_US
dc.contributor.authorWen, Charles H. -P.en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.date.accessioned2018-08-21T05:53:14Z
dc.date.available2018-08-21T05:53:14Z
dc.date.issued2017-12-01en_US
dc.description.abstractHotspots occur frequently in 3D multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. We present a new thermally constrained task scheduler based on a thermal-pattern-aware voltage assignment (TPAVA) to reduce hotspots in and optimize the performance of 3D-MCPs. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different initial operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. The proposed task scheduler consists of an on-line allocation strategy and a new voltage-scaling strategy. In particular, the proposed on-line allocation strategy uses the temperature-variation rates of the cores and takes into two important thermal behaviors of 3D-MCPs that can effectively minimize occurrences of hotspots in both thermally homogeneous and heterogeneous 3D-MCPs. Furthermore, a new vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs is used to handle thermal emergencies. Experimental results indicate that, when compared to a previous online thermally constrained task scheduler, the proposed task scheduler can reduce hotspot occurrences by approximately 66% (71%) and improve throughput by approximately 8% (2%) in thermally homogeneous (heterogeneous) 3D-MCPs. These results indicate that the proposed task scheduler is an effective technique for suppressing hotspot occurrences and optimizing throughput for 3D-MCPs subject to thermal constraints.en_US
dc.identifier.doi10.1587/transfun.E100.A.2901en_US
dc.identifier.issn1745-1337en_US
dc.identifier.journalIEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCESen_US
dc.identifier.urihttp://dx.doi.org/10.1587/transfun.E100.A.2901en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/144426
dc.identifier.wosnumberWOS:000423266000041en_US
dc.language.isoen_USen_US
dc.subjecton-line task scheduleren_US
dc.subject3D multi-core processorsen_US
dc.subjectthermally homogeneous and heterogeneous floorplansen_US
dc.subjecthotspotsen_US
dc.subjectvoltage assignmenten_US
dc.titleAn Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processorsen_US
dc.typeArticleen_US

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