A compact 12-bit DAC with novel bias scheme
| dc.citation.issue | 17 | en_US |
| dc.citation.volume | 11 | en_US |
| dc.citation.woscount | 0 | en_US |
| dc.contributor.author | Chou, Fang-Ting | en_US |
| dc.contributor.author | Hung, Chung-Chih | en_US |
| dc.contributor.department | 電機資訊學士班 | zh_TW |
| dc.contributor.department | Undergraduate Honors Program of Electrical Engineering and Computer Science | en_US |
| dc.date.accessioned | 2015-07-21T11:20:54Z | |
| dc.date.available | 2015-07-21T11:20:54Z | |
| dc.date.issued | 2014-01-01 | en_US |
| dc.description.abstract | A compact and low-power design of a 12-bit binary-weighted current-steering DAC is presented. Instead of 4096 unit current cells, the proposed design uses 192 unit current sources with two reference currents. The silicon area of the generation circuit of two reference currents is very compact as well. The area of the total current source arrays is smaller than four times the area of 6-bit current source arrays, which has significantly reduced the dimension of the analog part of a conventional 12-bit DAC. The proposed DAC achieves 400 MS/s update rate and consumes 38.7 mW from single 1.8 V supply. | en_US |
| dc.identifier.doi | 10.1587/elex.11.20140572 | en_US |
| dc.identifier.issn | 1349-2543 | en_US |
| dc.identifier.journal | IEICE ELECTRONICS EXPRESS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1587/elex.11.20140572 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/124164 | |
| dc.identifier.wosnumber | WOS:000344925800011 | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | digital-to-analog converter | en_US |
| dc.subject | DAC | en_US |
| dc.subject | compact area | en_US |
| dc.title | A compact 12-bit DAC with novel bias scheme | en_US |
| dc.type | Article | en_US |