Cycle time estimation for wafer fab with engineering lots
| dc.citation.epage | 118 | en_US |
| dc.citation.issue | 2 | en_US |
| dc.citation.spage | 105 | en_US |
| dc.citation.volume | 34 | en_US |
| dc.citation.woscount | 15 | |
| dc.contributor.author | Chung, SH | en_US |
| dc.contributor.author | Huang, HW | en_US |
| dc.contributor.department | 工業工程與管理學系 | zh_TW |
| dc.contributor.department | Department of Industrial Engineering and Management | en_US |
| dc.date.accessioned | 2014-12-08T15:42:49Z | |
| dc.date.available | 2014-12-08T15:42:49Z | |
| dc.date.issued | 2002-02-01 | en_US |
| dc.description.abstract | Due to the interaction between the process complexity and equipment diversity in a wafer fab, it is rather difficult to estimate the material flow time of wafer lots. Facing competition, it is common for a wafer fab to produce a certain quantity of engineering lots. However, introducing engineering lots into the factory will increase the complexity of the material flow control and the difficulty in cycle time estimation. The purpose of this paper is to develop cycle time estimation algorithms for a wafer fab by analyzing the material flow characteristics. Simulation results have shown that the algorithm is capable of generating satisfactory cycle time estimations with or without existing engineering lots. | en_US |
| dc.identifier.doi | 10.1023/A:1011935728647 | en_US |
| dc.identifier.issn | 0740-817X | en_US |
| dc.identifier.journal | IIE TRANSACTIONS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1023/A:1011935728647 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/29030 | |
| dc.identifier.wosnumber | WOS:000171291800002 | |
| dc.language.iso | en_US | en_US |
| dc.title | Cycle time estimation for wafer fab with engineering lots | en_US |
| dc.type | Article | en_US |