A dynamic scaling FFT processor for DVB-T applications
| dc.citation.epage | 2013 | en_US |
| dc.citation.issue | 11 | en_US |
| dc.citation.spage | 2005 | en_US |
| dc.citation.volume | 39 | en_US |
| dc.citation.woscount | 48 | |
| dc.contributor.author | Lin, YW | en_US |
| dc.contributor.author | Liu, HY | en_US |
| dc.contributor.author | Lee, CY | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:37:21Z | |
| dc.date.available | 2014-12-08T15:37:21Z | |
| dc.date.issued | 2004-11-01 | en_US |
| dc.description.abstract | This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer 1 are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-mum single-poly six-metal CMOS process with core area of 4.84 mm(2). Power dissipation is about 25.2 mW at 20 MHz. | en_US |
| dc.identifier.doi | 10.1109/JSSC.2004.835815 | en_US |
| dc.identifier.issn | 0018-9200 | en_US |
| dc.identifier.journal | IEEE JOURNAL OF SOLID-STATE CIRCUITS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/JSSC.2004.835815 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/25689 | |
| dc.identifier.wosnumber | WOS:000224692400021 | |
| dc.language.iso | en_US | en_US |
| dc.subject | DVB-T | en_US |
| dc.subject | fast Fourier transform (FFT) | en_US |
| dc.subject | orthogonal frequency division multiplexing (OFDM) | en_US |
| dc.title | A dynamic scaling FFT processor for DVB-T applications | en_US |
| dc.type | Article | en_US |