Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits

Abstract

An impedance-isolation technique is proposed tor on-chip ESD protection design tor radio-frequency (RF) integrated circuits (ICs), Which has been successfully verified in a 0.25-mu m CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequently of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore. the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S(21)-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation techniques have been experimentally measured and compared, to those with the conventional double-diodes ESD Protection scheme. The proposed impedance-isolation technique had been demonstrated to he suitable for on-chip ESD protection design for RF ICs.