Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

Abstract

This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 32 x 32, two 16 x 16 or four 8 x 8 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-V(t) standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-V(t) standard cell library.