A STUDY ON BILATERAL LATCH-UP SELF-TRIGGERING IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR PROTECTION CIRCUITS
| dc.citation.epage | 77 | en_US |
| dc.citation.issue | 1A | en_US |
| dc.citation.spage | 75 | en_US |
| dc.citation.volume | 33 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | HUANG, HS | en_US |
| dc.contributor.author | CHANG, CY | en_US |
| dc.contributor.author | CHEN, KL | en_US |
| dc.contributor.author | LIU, IO | en_US |
| dc.contributor.author | HSU, CC | en_US |
| dc.contributor.author | LIN, JK | en_US |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:04:13Z | |
| dc.date.available | 2014-12-08T15:04:13Z | |
| dc.date.issued | 1994-01-01 | en_US |
| dc.description.abstract | The results of serial studies on the behavior of bilateral latch-up in complementary metal-oxide-semiconductor field effect transistor (CMOS) protection circuits are presented. Bilateral latch-up self-triggering resulting from serial resistance or serial inductance on V-dd or V-ss is discussed. Optimizing the layout and design of output buffers to improve product performance and reliability is also recommended. The studies on the behavior of bilateral latch-up in CMOS protection circuits are increasingly important since low-power applications are the future trend. | en_US |
| dc.identifier.doi | 10.1143/JJAP.33.75 | en_US |
| dc.identifier.issn | 0021-4922 | en_US |
| dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1143/JJAP.33.75 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/2715 | |
| dc.identifier.wosnumber | WOS:A1994MV67700014 | |
| dc.language.iso | en_US | en_US |
| dc.subject | VLSI | en_US |
| dc.subject | CMOS | en_US |
| dc.subject | OUTPUT BUFFER | en_US |
| dc.subject | LATCH-UP | en_US |
| dc.subject | DIAC | en_US |
| dc.subject | SCR | en_US |
| dc.subject | BILATERAL | en_US |
| dc.title | A STUDY ON BILATERAL LATCH-UP SELF-TRIGGERING IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR PROTECTION CIRCUITS | en_US |
| dc.type | Article | en_US |