Active Guard Ring to Improve Latch-Up Immunity
| dc.citation.epage | 4152 | en_US |
| dc.citation.issue | 12 | en_US |
| dc.citation.spage | 4145 | en_US |
| dc.citation.volume | 61 | en_US |
| dc.citation.woscount | 0 | en_US |
| dc.contributor.author | Tsai, Hui-Wen | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2015-07-21T11:21:14Z | |
| dc.date.available | 2015-07-21T11:21:14Z | |
| dc.date.issued | 2014-12-01 | en_US |
| dc.description.abstract | A new design concept named as active guard ring and related circuit implementation to improve the latch-up immunity of ICs are proposed. Using additional sensing circuit and active buffer to turn ON the electrostatic discharge (ESD) protection transistors, the large-dimensional ESD (or I/O) devices can provide or receive extra compensation current to the negative or positive current perturbation during the latch-up current test. The new proposed solution has been verified in 0.6-mu m 5 V process to have much higher latch-up resistance compared with the conventional prevention method of guard ring in CMOS technology. | en_US |
| dc.identifier.doi | 10.1109/TED.2014.2363171 | en_US |
| dc.identifier.issn | 0018-9383 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/TED.2014.2363171 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/124102 | |
| dc.identifier.wosnumber | WOS:000346573600030 | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | Electrostatic discharge (ESD) protection | en_US |
| dc.subject | guard ring | en_US |
| dc.subject | latchup | en_US |
| dc.title | Active Guard Ring to Improve Latch-Up Immunity | en_US |
| dc.type | Article | en_US |