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Shallow-trench isolation with raised-field-oxide structure

dc.citation.epage1084en_US
dc.citation.issue3Aen_US
dc.citation.spage1080en_US
dc.citation.volume39en_US
dc.citation.woscount2
dc.contributor.authorChen, CMen_US
dc.contributor.authorChang, CYen_US
dc.contributor.authorChou, JWen_US
dc.contributor.authorLur, Wen_US
dc.contributor.authorSun, SWen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:45:38Z
dc.date.available2014-12-08T15:45:38Z
dc.date.issued2000-03-01en_US
dc.description.abstractThis paper describes a novel shallow-trench isolation (STI) structure to suppress the corner metal-oxide semiconductor field-effect transistor (MOSFET) inherent to trench isolation. A gate oxide and a thin polysilicon layer are first processed, and are then followed by the STI process. With this raised-field-oxide structure, the anomalous subthreshold conduction of the shallow-trench isolated MOSFETs due to electric-field crowding at the active edge has been successfully eliminated. No inverse-narrow-width effect is observed as the device width has been scaled down to 0.3 mu m. The raised-field-oxide structure provides a larger process margin for planarization, and good device characteristics were achieved by this novel STI structure.en_US
dc.identifier.doi10.1143/JJAP.39.1080en_US
dc.identifier.issn0021-4922en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERSen_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.39.1080en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/30707
dc.identifier.wosnumberWOS:000086705600019
dc.language.isoen_USen_US
dc.subjectSTIen_US
dc.subjectraised field oxideen_US
dc.subjectoxide recessen_US
dc.titleShallow-trench isolation with raised-field-oxide structureen_US
dc.typeArticleen_US

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