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Monolithic 3D CMOS Using Layered Semiconductors

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dc.citation.epage+en_US
dc.citation.issue13en_US
dc.citation.spage2547en_US
dc.citation.volume28en_US
dc.contributor.authorSachid, Angada B.en_US
dc.contributor.authorTosun, Mahmuten_US
dc.contributor.authorDesai, Sujay B.en_US
dc.contributor.authorHsu, Ching-Yien_US
dc.contributor.authorLien, Der-Hsienen_US
dc.contributor.authorMadhvapathy, Surabhi R.en_US
dc.contributor.authorChen, Yu-Zeen_US
dc.contributor.authorHettick, Marken_US
dc.contributor.authorKang, Jeong Seuken_US
dc.contributor.authorZeng, Yupingen_US
dc.contributor.authorHe, Jr-Hauen_US
dc.contributor.authorChang, Edward Yien_US
dc.contributor.authorChueh, Yu-Lunen_US
dc.contributor.authorJavey, Alien_US
dc.contributor.authorHu, Chenmingen_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.date.accessioned2017-04-21T06:56:30Z
dc.date.available2017-04-21T06:56:30Z
dc.date.issued2016-04-06en_US
dc.description.abstractMonolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications.en_US
dc.identifier.doi10.1002/adma.201505113en_US
dc.identifier.issn0935-9648en_US
dc.identifier.journalADVANCED MATERIALSen_US
dc.identifier.urihttp://dx.doi.org/10.1002/adma.201505113en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/133422
dc.identifier.wosnumberWOS:000373292700008en_US
dc.language.isoen_USen_US
dc.titleMonolithic 3D CMOS Using Layered Semiconductorsen_US

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