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Memory device application of wide-channel in-plane gate transistors with type-II GaAsSb-capped InAs quantum dots

dc.citation.epageen_US
dc.citation.issue14en_US
dc.citation.volume103en_US
dc.citation.woscount1
dc.contributor.authorLiao, Yu-Anen_US
dc.contributor.authorChao, Yi-Kaien_US
dc.contributor.authorChang, Shu-Weien_US
dc.contributor.authorChang, Wen-Haoen_US
dc.contributor.authorChyi, Jen-Innen_US
dc.contributor.authorLin, Shih-Yenen_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department光電工程學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentDepartment of Photonicsen_US
dc.date.accessioned2014-12-08T15:33:04Z
dc.date.available2014-12-08T15:33:04Z
dc.date.issued2013-09-30en_US
dc.description.abstractWe demonstrate room-temperature electron charging/discharging phenomena of InAs quantum dots using wide-channel in-plane gate transistors. The device based on type-II GaAsSb-capped InAs quantum dots exhibits both the longer charging and discharging times than those of the type-I counterpart with GaAs capping layers. The slow charge relaxation of GaAsSb-capped InAs quantum dots and simple architecture of in-plane gate transistors reveal the potential of this device architecture for practical memory applications. (C) 2013 AIP Publishing LLC.en_US
dc.identifier.doi10.1063/1.4824067en_US
dc.identifier.issn0003-6951en_US
dc.identifier.journalAPPLIED PHYSICS LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1063/1.4824067en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/23019
dc.identifier.wosnumberWOS:000325488500117
dc.language.isoen_USen_US
dc.titleMemory device application of wide-channel in-plane gate transistors with type-II GaAsSb-capped InAs quantum dotsen_US
dc.typeArticleen_US

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