Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology
| dc.citation.epage | 1049 | en_US |
| dc.citation.issue | 7 | en_US |
| dc.citation.spage | 1042 | en_US |
| dc.citation.volume | 46 | en_US |
| dc.citation.woscount | 2 | |
| dc.contributor.author | Chen, SH | en_US |
| dc.contributor.author | Ker, MD | en_US |
| dc.contributor.department | 電機學院 | zh_TW |
| dc.contributor.department | College of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:16:16Z | |
| dc.date.available | 2014-12-08T15:16:16Z | |
| dc.date.issued | 2006-07-01 | en_US |
| dc.description.abstract | Latchup failure which occurred at only one output pin of a power controller IC product is investigated in this work. The special design requirement of the internal circuits causes the parasitic diode that is inherent between the n-well and p-substrate to be a triggering source of the latchup, occurrence in this IC. The parasitic diode of the internal PMOS was easily turned on by an anomalous external signal to trigger the neighbor parasitic Silicon Controlled Rectifier (SCR) path which causes latchup event in the CMOS IC product. Some solutions to overcome this latchup failure have been also proposed in this paper. (c) 2005 Elsevier Ltd. All rights reserved. | en_US |
| dc.identifier.doi | 10.1016/j.microrel.2005.09.009 | en_US |
| dc.identifier.issn | 0026-2714 | en_US |
| dc.identifier.journal | MICROELECTRONICS RELIABILITY | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1016/j.microrel.2005.09.009 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/12059 | |
| dc.identifier.wosnumber | WOS:000238115900003 | |
| dc.language.iso | en_US | en_US |
| dc.title | Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology | en_US |
| dc.type | Article | en_US |