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Novel yield model for integrated circuits with clustered defects

dc.citation.epage2341en_US
dc.citation.issue4en_US
dc.citation.spage2334en_US
dc.citation.volume34en_US
dc.citation.woscount5
dc.contributor.authorTong, Lee-Ingen_US
dc.contributor.authorChao, Li-Changen_US
dc.contributor.department工業工程與管理學系zh_TW
dc.contributor.departmentDepartment of Industrial Engineering and Managementen_US
dc.date.accessioned2014-12-08T15:12:11Z
dc.date.available2014-12-08T15:12:11Z
dc.date.issued2008-05-04en_US
dc.description.abstractAs wafer sizes increase, the clustering phenomenon of defects increases. Clustered defects cause the conventional Poisson yield model underestimate actual wafer yield, as defects are no longer uniformly distributed over a wafer. Although some yield models, such as negative binomial or compound Poisson models, consider the effects of defect clustering on yield prediction, these models have some drawbacks. This study presents a novel yield model that employs General Regression Neural Network (GRNN) to predict wafer yield for integrated circuits (IC) with clustered defects. The proposed method utilizes five relevant variables as input for the GRNN yield model. A simulated case is applied to demonstrate the effectiveness of the proposed model. (c) 2007 Elsevier Ltd. All rights reserved.en_US
dc.identifier.doi10.1016/j.eswa.2007.03.013en_US
dc.identifier.issn0957-4174en_US
dc.identifier.journalEXPERT SYSTEMS WITH APPLICATIONSen_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.eswa.2007.03.013en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/9348
dc.identifier.wosnumberWOS:000253521900011
dc.language.isoen_USen_US
dc.subjectclustered defectsen_US
dc.subjectgeneral regression neural networken_US
dc.subjectICen_US
dc.subjectpatternen_US
dc.subjectyield modelen_US
dc.titleNovel yield model for integrated circuits with clustered defectsen_US
dc.typeArticleen_US

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