Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress
| dc.citation.epage | en_US | |
| dc.citation.issue | 25 | en_US |
| dc.citation.volume | 95 | en_US |
| dc.citation.woscount | 1 | |
| dc.contributor.author | Hsieh, Zhen-Ying | en_US |
| dc.contributor.author | Wang, Mu-Chun | en_US |
| dc.contributor.author | Chen, Shuang-Yuan | en_US |
| dc.contributor.author | Chen, Chih | en_US |
| dc.contributor.author | Huang, Heng-Sheng | en_US |
| dc.contributor.department | 材料科學與工程學系 | zh_TW |
| dc.contributor.department | Department of Materials Science and Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:08:03Z | |
| dc.date.available | 2014-12-08T15:08:03Z | |
| dc.date.issued | 2009-12-21 | en_US |
| dc.description.abstract | In this work, a metrology was proposed to realize the distribution of fixed oxide trapped charges and grain boundary trapped states. The (continuous-wave green laser crystallization) n-channel thin-film transistors (TFTs) were forced by dc voltage stress, V(G)=V(D). The gate-to-drain capacitance, C(GD) -V(G), with varying frequency of applied small signal was developed. To probe the distribution of these defects, the difference (initial capacitance values minus stressed capacitance values) of C(GD) -V(G) with different frequencies was precisely studied. (C) 2009 American Institute of Physics. [doi:10.1063/1.3275728] | en_US |
| dc.identifier.doi | 10.1063/1.3275728 | en_US |
| dc.identifier.issn | 0003-6951 | en_US |
| dc.identifier.journal | APPLIED PHYSICS LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1063/1.3275728 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/6306 | |
| dc.identifier.wosnumber | WOS:000273037700060 | |
| dc.language.iso | en_US | en_US |
| dc.title | Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress | en_US |
| dc.type | Article | en_US |