DESIGN OF PSEUDOEXHAUSTIVE TESTABLE PLA WITH LOW OVERHEAD
| dc.citation.epage | 891 | en_US |
| dc.citation.issue | 7 | en_US |
| dc.citation.spage | 887 | en_US |
| dc.citation.volume | 42 | en_US |
| dc.citation.woscount | 1 | |
| dc.contributor.author | SHEN, WZ | en_US |
| dc.contributor.author | HWANG, GH | en_US |
| dc.contributor.author | HSU, WJ | en_US |
| dc.contributor.author | JAN, YJ | en_US |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:04:26Z | |
| dc.date.available | 2014-12-08T15:04:26Z | |
| dc.date.issued | 1993-07-01 | en_US |
| dc.description.abstract | The pseudoexhaustive testing (PET) scheme is a economic approach to test a large embedded programmable logic array (PIA). In this paper, we propose an efficient algorithm named low overhead PET (LOPET) to partition the product lines. By applying our algorithm, both the area overhead and test length are reduced significantly. | en_US |
| dc.identifier.doi | 10.1109/12.237730 | en_US |
| dc.identifier.issn | 0018-9340 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/12.237730 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/2948 | |
| dc.identifier.wosnumber | WOS:A1993MB58300012 | |
| dc.language.iso | en_US | en_US |
| dc.subject | BUILT-IN SELF-TEST | en_US |
| dc.subject | DESIGN FOR TESTABILITY | en_US |
| dc.subject | PROGRAMMABLE LOGIC ARRAY | en_US |
| dc.subject | PSEUDOEXHAUSTIVE TESTING | en_US |
| dc.title | DESIGN OF PSEUDOEXHAUSTIVE TESTABLE PLA WITH LOW OVERHEAD | en_US |
| dc.type | Letter | en_US |