New test structure to monitor contact-to-poly leakage in sub-90 nm CMOS technologies
| dc.citation.epage | 247 | en_US |
| dc.citation.issue | 2 | en_US |
| dc.citation.spage | 244 | en_US |
| dc.citation.volume | 21 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | King, Ming-Chu | en_US |
| dc.contributor.author | Chin, Albert | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:12:16Z | |
| dc.date.available | 2014-12-08T15:12:16Z | |
| dc.date.issued | 2008-05-01 | en_US |
| dc.description.abstract | The high leakage or even direct short between contact and gate is a serious problem after the feature sizes are shrunk to 65-nm technology and beyond. However, there is no suitable test structure to effectively monitor the leakage current between them. We have designed a new test structure which can eliminate the drawbacks of existing test structures and effectively monitor the leakage current between contact and gate electrode in state-of-the-art CMOS process technology. | en_US |
| dc.identifier.doi | 10.1109/TSM.2008.2000267 | en_US |
| dc.identifier.issn | 0894-6507 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/TSM.2008.2000267 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/9435 | |
| dc.identifier.wosnumber | WOS:000255869600017 | |
| dc.language.iso | en_US | en_US |
| dc.subject | contact | en_US |
| dc.subject | gate | en_US |
| dc.subject | leakage current | en_US |
| dc.subject | test structure | en_US |
| dc.title | New test structure to monitor contact-to-poly leakage in sub-90 nm CMOS technologies | en_US |
| dc.type | Article | en_US |