Delayed precise invalidation - A software cache coherence scheme
| dc.citation.epage | 344 | en_US |
| dc.citation.issue | 5 | en_US |
| dc.citation.spage | 337 | en_US |
| dc.citation.volume | 143 | en_US |
| dc.citation.woscount | 1 | |
| dc.contributor.author | Hwang, TS | en_US |
| dc.contributor.author | Lu, NP | en_US |
| dc.contributor.author | Chung, CP | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.date.accessioned | 2014-12-08T15:02:24Z | |
| dc.date.available | 2014-12-08T15:02:24Z | |
| dc.date.issued | 1996-09-01 | en_US |
| dc.description.abstract | Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence scheme named 'delayed precise invalidation' (DPI). DPI is based on compiler-time markings of references and a hardware local invalidation of stale data in parallel and selectively. With a small amount of additional hardware and a small set of cache management instructions, this scheme provides more cacheability and allows invalidation of partial elements in an array, overcoming some inefficiencies and deficiencies of previous software cache coherence schemes. | en_US |
| dc.identifier.issn | 1350-2387 | en_US |
| dc.identifier.journal | IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/1073 | |
| dc.identifier.wosnumber | WOS:A1996VP48100014 | |
| dc.language.iso | en_US | en_US |
| dc.subject | cache coherence | en_US |
| dc.subject | compilers | en_US |
| dc.subject | invalidation | en_US |
| dc.title | Delayed precise invalidation - A software cache coherence scheme | en_US |
| dc.type | Article | en_US |