Performance and characteristics of double layer porous silicon oxide resistance random access memory
| dc.citation.epage | en_US | |
| dc.citation.issue | 25 | en_US |
| dc.citation.volume | 102 | en_US |
| dc.citation.woscount | 15 | |
| dc.contributor.author | Tsai, Tsung-Ming | en_US |
| dc.contributor.author | Chang, Kuan-Chang | en_US |
| dc.contributor.author | Zhang, Rui | en_US |
| dc.contributor.author | Chang, Ting-Chang | en_US |
| dc.contributor.author | Lou, J. C. | en_US |
| dc.contributor.author | Chen, Jung-Hui | en_US |
| dc.contributor.author | Young, Tai-Fa | en_US |
| dc.contributor.author | Tseng, Bae-Heng | en_US |
| dc.contributor.author | Shih, Chih-Cheng | en_US |
| dc.contributor.author | Pan, Yin-Chih | en_US |
| dc.contributor.author | Chen, Min-Chen | en_US |
| dc.contributor.author | Pan, Jhih-Hong | en_US |
| dc.contributor.author | Syu, Yong-En | en_US |
| dc.contributor.author | Sze, Simon M. | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:31:21Z | |
| dc.date.available | 2014-12-08T15:31:21Z | |
| dc.date.issued | 2013-06-24 | en_US |
| dc.description.abstract | A bilayer resistive switching memory device with an inserted porous silicon oxide layer is investigated in this letter. Compared with single Zr:SiOx layer structure, Zr: SiOx/ porous SiOx structure outperforms from various aspects, including low operating voltages, tighter distributions of set voltage, higher stability of both low resistance state and high resistance state, and satisfactory endurance characteristics. Electric field simulation by COMSOL (TM) Multiphysics is applied, which corroborates that intensive electric field around the pore in porous SiOx layer guides the conduction of electrons. The constraint of conduction path leads to better stabilization and prominent performance of bilayer resistive switching devices. (C) 2013 AIP Publishing LLC. | en_US |
| dc.identifier.doi | 10.1063/1.4812474 | en_US |
| dc.identifier.issn | 0003-6951 | en_US |
| dc.identifier.journal | APPLIED PHYSICS LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1063/1.4812474 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/22283 | |
| dc.identifier.wosnumber | WOS:000321145200095 | |
| dc.language.iso | en_US | en_US |
| dc.title | Performance and characteristics of double layer porous silicon oxide resistance random access memory | en_US |
| dc.type | Article | en_US |