ESD Avoiding Circuits for Solving OTP Memory Falsely Programmed Issues

Abstract

One-time program (OTP) memories are programmed for memory design without electrostatic discharge (ESD) stresses. However, in reality, ESD events are not selective and thus ESD currents can falsely program OTP memory cells. Many integrated circuit (IC) designers focus only on improving OTP memory control architectures to avoid memory being falsely programmed without mentioning the ESD-introduced memory errors. This article investigates a new ESD architecture and novel ESD avoiding circuits, aiming to solve ESD-introduced memory falsely programmed issues. It should be noted that this article focuses on ESD circuit designs to protect OTP memory instead of OTP control architectures. With such new ESD schemes, our prototype circuits have demonstrated that memory cells can indeed be programmed at IC program mode without ESD stresses.