Impacts of gate structure on dynamic threshold SOI nMOSFETs
| dc.citation.epage | 499 | en_US |
| dc.citation.issue | 8 | en_US |
| dc.citation.spage | 497 | en_US |
| dc.citation.volume | 23 | en_US |
| dc.citation.woscount | 10 | |
| dc.contributor.author | Lo, WC | en_US |
| dc.contributor.author | Chang, SJ | en_US |
| dc.contributor.author | Chang, CY | en_US |
| dc.contributor.author | Chao, TS | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:42:07Z | |
| dc.date.available | 2014-12-08T15:42:07Z | |
| dc.date.issued | 2002-08-01 | en_US |
| dc.description.abstract | The effects of different substrate-contact structures (T-gate and H-gate) dynamic threshold voltage silicon-on-insulator (SOI) nMOSFETs (DTMOS) have been investigated. It is found that H-gate structure devices have higher driving current than T-gate under DTMOS-mode operation. This is because H-gate SOI devices have larger body effect factor (gamma), inducing a lager reduction of threshold voltage. Besides, it is found that drain-induced-barrier-lowering (DIBL) is dramatically reduced for both T-gate and H-gate structure devices when devices are operated under DTMOS-mode. | en_US |
| dc.identifier.doi | 10.1109/LED.2002.801334 | en_US |
| dc.identifier.issn | 0741-3106 | en_US |
| dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/LED.2002.801334 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/28617 | |
| dc.identifier.wosnumber | WOS:000177207300018 | |
| dc.language.iso | en_US | en_US |
| dc.subject | dynamic threshold MOS (DTMOS) | en_US |
| dc.subject | H-gate | en_US |
| dc.subject | silicon-on-insulator (SOI) | en_US |
| dc.subject | T-gate | en_US |
| dc.title | Impacts of gate structure on dynamic threshold SOI nMOSFETs | en_US |
| dc.type | Article | en_US |