Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

Abstract

For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The ID degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which holetrap-induced V-T is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device ID degradation. In addition, the V-T rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N-2 content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.