Well supply voltage effect on escape current of guard rings in epitaxial CMOS technology

Abstract

An n-well guard ring dual collector structure formed on an epitaxial substrate has been characterized and simulated. The measured I-V characteristics have exhibited that a reduction of well supply voltage from 5.0 to 1.0 V causes an increase in the escape current into the outer well by a factor of about 14, while the base and inner guard ring collector currents are hardly changed. This will influence neighboring latchup susceptibility substantially. This experimental observation can provide a new evidence of the published theory responsible for the escape current: the injected minority carriers flow through a quasi-neutral layer between the upper collecting plate and the bottom high/low junction reflecting plate. Based on this theory actual epitaxial layer thickness can be extracted with low guard ring voltages as well. Published by Elsevier Science Ltd. All rights reserved.