THE BEHAVIOR OF BILATERAL LATCH-UP TRIGGERING IN VLSI ELECTROSTATIC DISCHARGE DAMAGE PROTECTION CIRCUITS

Abstract

A new latch-up phenomenon that shows symmetrical diac I-V characteristics has been discovered recently. Electrical measurements show that a diac parasitic semiconductor-controlled-rectifier (SCR) device can exist between two adjacent electro static discharge damage (ESD) protection circuits or output buffers. The SCR consists of two parasitic P-N-P-N paths and can easily induce a localized SCR latch-up between two adjacent input or output terminals. This is not similar to traditional latch-up that creates a parasitic P-N-P-N path between power supply and ground pins, but is a new bilateral latch-up path between two adjacent input and output pins. A new latch-up failure mode due to this diac structure, which creates a bilateral path during temperature humidity bias (THB) testing, is discussed. Some suggestions regarding the improvement of this diac latch-up degradation are proposed. Advanced analyses and modeling are also presented in this paper. The modified diac latch-up lumped element model successfull explains this phenomenon.