SUPPRESSION OF THE BORON PENETRATION INDUCED SI/SIO2 INTERFACE DEGRADATION BY USING A STACKED-AMORPHOUS-SILICON FILM AS THE GATE STRUCTURE FOR PMOSFET
| dc.citation.epage | 162 | en_US |
| dc.citation.issue | 5 | en_US |
| dc.citation.spage | 160 | en_US |
| dc.citation.volume | 15 | en_US |
| dc.citation.woscount | 15 | |
| dc.contributor.author | WU, SL | en_US |
| dc.contributor.author | LEE, CL | en_US |
| dc.contributor.author | LEI, TF | en_US |
| dc.contributor.author | CHEN, JF | en_US |
| dc.contributor.author | CHEN, LJ | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:04:01Z | |
| dc.date.available | 2014-12-08T15:04:01Z | |
| dc.date.issued | 1994-05-01 | en_US |
| dc.description.abstract | This letter reports that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO2 interface. An atomically flat Si/SiO2 interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p+ poly-Si gate MOS devices even the annealing temperature is as high as 1000-degrees-C. | en_US |
| dc.identifier.doi | 10.1109/55.291600 | en_US |
| dc.identifier.issn | 0741-3106 | en_US |
| dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/55.291600 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/2525 | |
| dc.identifier.wosnumber | WOS:A1994NP23600006 | |
| dc.language.iso | en_US | en_US |
| dc.title | SUPPRESSION OF THE BORON PENETRATION INDUCED SI/SIO2 INTERFACE DEGRADATION BY USING A STACKED-AMORPHOUS-SILICON FILM AS THE GATE STRUCTURE FOR PMOSFET | en_US |
| dc.type | Article | en_US |