The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memory
| dc.citation.epage | en_US | |
| dc.citation.issue | 18 | en_US |
| dc.citation.spage | en_US | |
| dc.citation.volume | 97 | en_US |
| dc.contributor.author | Ho, Y. H. | en_US |
| dc.contributor.author | Chung, Steve S. | en_US |
| dc.contributor.author | Chen, H. H. | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:47:46Z | |
| dc.date.available | 2014-12-08T15:47:46Z | |
| dc.date.issued | 2010-11-01 | en_US |
| dc.description.abstract | The charge loss mechanism of a two-bit wrapped-gate nitride storage nonvolatile memory is investigated. From retention measurements, it was shown that both vertical and lateral charge loss coexist. As a result of the misalignment of carriers, the lateral charge loss was caused by the hole accumulation near the junction and migrating toward the channel. By using a scaling of the word-gate length or a substrate-transient hot hole erase scheme, the charge loss in the lateral direction can be suppressed. Also, from the retention test, the latter scheme, substrate-transient hot hole (STHH), has a window independent of the word-gate length, which is better for the device scaling. (C) 2010 American Institute of Physics. [doi:10.1063/1.3508956] | en_US |
| dc.identifier.doi | 10.1063/1.3508956 | en_US |
| dc.identifier.issn | 0003-6951 | en_US |
| dc.identifier.journal | APPLIED PHYSICS LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1063/1.3508956 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/31951 | |
| dc.language.iso | en_US | en_US |
| dc.title | The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memory | en_US |
| dc.type | Article | en_US |