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A micro-architecture simulator for multimedia stream processor

dc.citation.epage771en_US
dc.citation.spage768en_US
dc.contributor.authorLin, Fang-Juen_US
dc.contributor.authorChiueh, Hermingen_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.date.accessioned2014-12-08T15:25:03Z
dc.date.available2014-12-08T15:25:03Z
dc.date.issued2006en_US
dc.description.abstractRecent research has proposed using stream processors for media applications. Since a programmable Stream Processor could utilize various hardware micro-architectures for diverse media applications, decision on a suitable micro-architectures to achieve efficiencies and hardware cost is critical. In this paper, a micro-architecture simulator for stream processor is implemented. The simulator evaluate the performance of media application executed on various micro-architectures, and then to analyze the utility rate of hardware and consumption of memory. By comparing the performance of media application executed on diverse micro-architectures, the optimized hardware micro-architecture can be determined for specific application and suitable micro-architecture of Stream Processor can be implemented on later VLSI for different targeting systems.en_US
dc.identifier.doi10.1109/ICECS.2006.379902en_US
dc.identifier.isbn978-1-4244-0394-3en_US
dc.identifier.journal2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ICECS.2006.379902en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/17422
dc.identifier.wosnumberWOS:000252489600192
dc.language.isoen_USen_US
dc.titleA micro-architecture simulator for multimedia stream processoren_US
dc.typeProceedings Paperen_US

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