AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS
| dc.citation.epage | 407 | en_US |
| dc.citation.issue | 4 | en_US |
| dc.citation.spage | 395 | en_US |
| dc.citation.volume | 29 | en_US |
| dc.citation.woscount | 1 | |
| dc.contributor.author | CHEN, MJ | en_US |
| dc.contributor.author | WU, CY | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | 工學院 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.contributor.department | College of Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:06:11Z | |
| dc.date.available | 2014-12-08T15:06:11Z | |
| dc.date.issued | 1986-04-01 | en_US |
| dc.identifier.issn | 0038-1101 | en_US |
| dc.identifier.journal | SOLID-STATE ELECTRONICS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/4760 | |
| dc.identifier.wosnumber | WOS:A1986A899500003 | |
| dc.language.iso | en_US | en_US |
| dc.title | AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS | en_US |
| dc.type | Article | en_US |
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