SIMPLIFYING SEQUENTIAL-CIRCUIT TEST-GENERATION
| dc.citation.epage | 38 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 28 | en_US |
| dc.citation.volume | 11 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | SHEU, ML | en_US |
| dc.contributor.author | LEE, CL | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:03:50Z | |
| dc.date.available | 2014-12-08T15:03:50Z | |
| dc.date.issued | 1994-09-01 | en_US |
| dc.description.abstract | Design for testability reduces testing costs for sequential circuits. The authors present a parity checker DFT scheme they have incorporated into a finite-state machine synthesis system. Generating tests for circuits synthesized according to this scheme becomes extremely simple. The derived test sequence very efficiently detects faults. | en_US |
| dc.identifier.issn | 0740-7475 | en_US |
| dc.identifier.journal | IEEE DESIGN & TEST OF COMPUTERS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/2362 | |
| dc.identifier.wosnumber | WOS:A1994PB47600004 | |
| dc.language.iso | en_US | en_US |
| dc.title | SIMPLIFYING SEQUENTIAL-CIRCUIT TEST-GENERATION | en_US |
| dc.type | Article | en_US |