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Fault diagnosis for linear analog circuits

dc.citation.epage494en_US
dc.citation.issue6en_US
dc.citation.spage483en_US
dc.citation.volume17en_US
dc.citation.woscount4
dc.contributor.authorLin, JWen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorSu, CCen_US
dc.contributor.authorChen, JEen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:44:22Z
dc.date.available2014-12-08T15:44:22Z
dc.date.issued2001en_US
dc.description.abstractThis paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs "diagnosing evaluators," which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as active faults in OP's.en_US
dc.identifier.doi10.1023/A:1012816621144en_US
dc.identifier.issn0923-8174en_US
dc.identifier.journalJOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONSen_US
dc.identifier.urihttp://dx.doi.org/10.1023/A:1012816621144en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/29968
dc.identifier.wosnumberWOS:000172279100003
dc.language.isoen_USen_US
dc.subjectfault diagnosisen_US
dc.subjectsignal flow graphen_US
dc.subjectdiagnosing evaluatorsen_US
dc.subjectun-powered networken_US
dc.titleFault diagnosis for linear analog circuitsen_US
dc.typeArticleen_US

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