Breakdown modes and their evolution in ultrathin gate oxide
| dc.citation.epage | 5963 | en_US |
| dc.citation.issue | 10 | en_US |
| dc.citation.spage | 5957 | en_US |
| dc.citation.volume | 41 | en_US |
| dc.citation.woscount | 5 | |
| dc.contributor.author | Lin, HC | en_US |
| dc.contributor.author | Lee, DY | en_US |
| dc.contributor.author | Huang, TY | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:41:52Z | |
| dc.date.available | 2014-12-08T15:41:52Z | |
| dc.date.issued | 2002-10-01 | en_US |
| dc.description.abstract | Post-breakdown current-voltage characteristics of metal-oxide-semiconductor (MOS) devices kith an ultrathin gate oxide layer have been carefully studied. Several breakdown modes were identified. Specifically, it was found that the typical soft-breakdown mode induced in an oxide lay er thinner than 3 nm is actually quite different from that in an oxide layer thicker than 3 nm. Based on these findings, we have also proposed a model to explain the evolution of different breakdown modes. The model takes into consideration the thermal runaway process at the breakdown moment, and is substantiated by a number of experimental findings. Impacts of each breakdown mode on device switching behavior are also discussed. | en_US |
| dc.identifier.issn | 0021-4922 | en_US |
| dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/28474 | |
| dc.identifier.wosnumber | WOS:000179893600014 | |
| dc.language.iso | en_US | en_US |
| dc.subject | ultrathin gate oxide | en_US |
| dc.subject | metal-oxide-semiconductor (MOS) | en_US |
| dc.subject | soft breakdown | en_US |
| dc.subject | hard breakdown | en_US |
| dc.title | Breakdown modes and their evolution in ultrathin gate oxide | en_US |
| dc.type | Article | en_US |