The extraction of MOSFET gate capacitance from S-parameter measurements
| dc.citation.epage | 1167 | en_US |
| dc.citation.issue | 8 | en_US |
| dc.citation.spage | 1163 | en_US |
| dc.citation.volume | 46 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Su, JG | en_US |
| dc.contributor.author | Wong, SC | en_US |
| dc.contributor.author | Chang, CY | en_US |
| dc.contributor.author | Huang, TY | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:42:09Z | |
| dc.date.available | 2014-12-08T15:42:09Z | |
| dc.date.issued | 2002-08-01 | en_US |
| dc.description.abstract | A new gate capacitance extraction method from S-parameter measurements is proposed. The distributed nature of MOS transistor and the in-series substrate resistance and in-parallel gate conductance are taken into consideration in the gate capacitance extraction by using high-frequency S-parameter measurements. The error due to dissipation factor can be more effectively reduced by this method, compared to the conventional C-V measurements. Successful extraction of gate capacitance from test transistors with designed test pads has been demonstrated. (C) 2002 Elsevier Science Ltd. All rights reserved. | en_US |
| dc.identifier.doi | 10.1016/S0038-1101(02)00022-9 | en_US |
| dc.identifier.issn | 0038-1101 | en_US |
| dc.identifier.journal | SOLID-STATE ELECTRONICS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1016/S0038-1101(02)00022-9 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/28645 | |
| dc.identifier.wosnumber | WOS:000177094400017 | |
| dc.language.iso | en_US | en_US |
| dc.title | The extraction of MOSFET gate capacitance from S-parameter measurements | en_US |
| dc.type | Article | en_US |