Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism
| dc.citation.epage | 283 | en_US |
| dc.citation.issue | 4 | en_US |
| dc.citation.spage | 281 | en_US |
| dc.citation.volume | 31 | en_US |
| dc.citation.woscount | 7 | |
| dc.contributor.author | Liao, Chia-Chun | en_US |
| dc.contributor.author | Chiang, Tsung-Yu | en_US |
| dc.contributor.author | Lin, Min-Chen | en_US |
| dc.contributor.author | Chao, Tien-Sheng | en_US |
| dc.contributor.department | 電子物理學系 | zh_TW |
| dc.contributor.department | Department of Electrophysics | en_US |
| dc.date.accessioned | 2014-12-08T15:07:06Z | |
| dc.date.available | 2014-12-08T15:07:06Z | |
| dc.date.issued | 2010-04-01 | en_US |
| dc.description.abstract | In this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should bemodulated from the point of view of stress shift rather than using the highest tensile film. | en_US |
| dc.identifier.doi | 10.1109/LED.2010.2041524 | en_US |
| dc.identifier.issn | 0741-3106 | en_US |
| dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/LED.2010.2041524 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/5571 | |
| dc.identifier.wosnumber | WOS:000276017000008 | |
| dc.language.iso | en_US | en_US |
| dc.subject | Contact etch-stop layer (CESL) | en_US |
| dc.subject | poly amorphization implantation (PAI) | en_US |
| dc.subject | strain | en_US |
| dc.subject | stress memorization technique (SMT) | en_US |
| dc.title | Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism | en_US |
| dc.type | Article | en_US |