Comment on "Generic universal switch blocks"
| dc.citation.epage | 95 | en_US |
| dc.citation.issue | 1 | en_US |
| dc.citation.spage | 93 | en_US |
| dc.citation.volume | 51 | en_US |
| dc.citation.woscount | 5 | |
| dc.contributor.author | Fan, HB | en_US |
| dc.contributor.author | Wu, YL | en_US |
| dc.contributor.author | Chang, YW | en_US |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.date.accessioned | 2014-12-08T15:42:55Z | |
| dc.date.available | 2014-12-08T15:42:55Z | |
| dc.date.issued | 2002-01-01 | en_US |
| dc.description.abstract | In the paper [5], the authors defined the well-structured symmetric switch block M-N,M-W and showed that M-N,M-W is universal for any pair of positive integers N and W, However, we find that this result is partially correct. Here, we show that, when N greater than or equal to 7, M-N,M-W is not universal for odd Ws (greater than or equal to 3) and it is universal for any even W. | en_US |
| dc.identifier.doi | 10.1109/12.980020 | en_US |
| dc.identifier.issn | 0018-9340 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/12.980020 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/29083 | |
| dc.identifier.wosnumber | WOS:000173862900008 | |
| dc.language.iso | en_US | en_US |
| dc.subject | field programmable gate array | en_US |
| dc.subject | universal switch block design | en_US |
| dc.subject | FPGA routing | en_US |
| dc.title | Comment on "Generic universal switch blocks" | en_US |
| dc.type | Article | en_US |