A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier

dc.citation.epage	2128	en_US
dc.citation.issue	10	en_US
dc.citation.spage	2122	en_US
dc.citation.volume	E86C	en_US
dc.citation.woscount	3
dc.contributor.author	Hsu, CC	en_US
dc.contributor.author	Wu, JT	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:40:13Z
dc.date.available	2014-12-08T15:40:13Z
dc.date.issued	2003-10-01	en_US
dc.description.abstract	A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 mum CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm(2) and dissipates 33mW from a single 2.5V supply.	en_US
dc.identifier.issn	0916-8524	en_US
dc.identifier.journal	IEICE TRANSACTIONS ON ELECTRONICS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/27463
dc.identifier.wosnumber	WOS:000185839500035
dc.language.iso	en_US	en_US
dc.subject	sample-and-hold circuits	en_US
dc.subject	switched-capacitor circuits	en_US
dc.subject	time-interleaved analog-to-digital converter	en_US
dc.title	A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier	en_US
dc.type	Article	en_US

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