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Low power resistive random access memory using interface-engineered dielectric stack of SiOx/a-Si/TiOy with 1D1R-like structure

dc.citation.epage143en_US
dc.citation.issue1en_US
dc.citation.spage139en_US
dc.citation.volume14en_US
dc.citation.woscount1
dc.contributor.authorCheng, Chun-Huen_US
dc.contributor.authorChou, K. I.en_US
dc.contributor.authorZheng, Zhi-Weien_US
dc.contributor.authorHsu, Hsiao-Hsuanen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:33:58Z
dc.date.available2014-12-08T15:33:58Z
dc.date.issued2014-01-01en_US
dc.description.abstractIn this study, we report a resistive random access memory (RRAM) using trilayer SiOx/a-Si/TiOy film structure. The low switching energy of <10 pJ, highly uniform current distribution (<13% variation), fast 50-ns speed and stable cycling endurance for 10(6) cycles are simultaneously achieved in this RRAM device. Such good performance can be ascribed to the use of interface-engineered dielectric stack with 1D1R-like structure. The SiOx tunnel barrier in contact with top Ni electrode to form diode-like rectifying element not only lowers self-compliance switching currents, but also improves cycling endurance, which is favorable for the application of high-density 3D memory. (C) 2013 Elsevier B. V. All rights reserved.en_US
dc.identifier.doi10.1016/j.cap.2013.10.019en_US
dc.identifier.issn1567-1739en_US
dc.identifier.journalCURRENT APPLIED PHYSICSen_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.cap.2013.10.019en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/23399
dc.identifier.wosnumberWOS:000328477900023
dc.language.isoen_USen_US
dc.subjectResistive random access memory (RRAM)en_US
dc.subjectSiO2en_US
dc.subjectTiO2en_US
dc.subjectCurrent distributionen_US
dc.titleLow power resistive random access memory using interface-engineered dielectric stack of SiOx/a-Si/TiOy with 1D1R-like structureen_US
dc.typeArticleen_US

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