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A HIGH-SPEED NEURAL ANALOG CIRCUIT FOR COMPUTING THE BIT-LEVEL TRANSFORM IMAGE-CODING

dc.citation.epage342en_US
dc.citation.issue3en_US
dc.citation.spage337en_US
dc.citation.volume37en_US
dc.citation.woscount1
dc.contributor.authorCHANG, PRen_US
dc.contributor.authorHWANG, KSen_US
dc.contributor.authorGONG, HMen_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.date.accessioned2014-12-08T15:05:11Z
dc.date.available2014-12-08T15:05:11Z
dc.date.issued1991-08-01en_US
dc.description.abstractThis paper presents a Hopfield-type neural network approach which leads to an analog circuit for implementing the bit-level transform image. Different from the conventional digital approach to image coding, the analog coding system would operate at a much higher speed and requires less hardware than digital system. In order to utilize the concept of neural net, the computation of a two-dimensional DCT-based transform coding should be reformulated as minimizing a quadratic nonlinear programming problem subject to the corresponding 2's complement binary variables of 2-D DCT coefficients. A novel Hopfield-type neural net with a number of graded-response neurons designed to perform the quadratic nonlinear programming would lead to such a solution in a time determined by RC time constants, not by algorithmic time complexity. A fourth order Runge-Kutta simulation is conducted to verify the performance of the proposed analog circuit. Experiments show that the circuit is quite robust and independent of parameter variations and the computation time of an 8 x 8 DCT is about 1ns for RC = 10(-8). In practice, programmable hybrid digital-analog MOS circuits are required to implement the neural-based DCT optimizer. The circuit techniques are based on extremely simple and programmable analog parameterized MOS modules with such attractive features as reconfigurability, input/output compatibility, and unrestricted fan-in/fan-out capability.1en_US
dc.identifier.doi10.1109/30.85534en_US
dc.identifier.issn0098-3063en_US
dc.identifier.journalIEEE TRANSACTIONS ON CONSUMER ELECTRONICSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/30.85534en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/3715
dc.identifier.wosnumberWOS:A1991GE54700025
dc.language.isoen_USen_US
dc.titleA HIGH-SPEED NEURAL ANALOG CIRCUIT FOR COMPUTING THE BIT-LEVEL TRANSFORM IMAGE-CODINGen_US
dc.typeArticleen_US

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