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Impact of Strain Layer on Gate Leakage and Interface-State for nMOSFETs Fabricated by Stress-Memorization Technique

dc.citation.epageII32en_US
dc.citation.issue1en_US
dc.citation.spageII30en_US
dc.citation.volume14en_US
dc.citation.woscount0
dc.contributor.authorLiao, Chia-Chunen_US
dc.contributor.authorLin, Min-Chenen_US
dc.contributor.authorChiang, Tsung-Yuen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.date.accessioned2014-12-08T15:38:10Z
dc.date.available2014-12-08T15:38:10Z
dc.date.issued2011en_US
dc.description.abstractThis paper investigates the impact of stress memorization on the interface-state for n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETS). We found that both the initial component of the deposited capping layer and the H released during annealing affected interface-state passivation. The annealed stress is responsible for degraded gate-leakage characteristics. Based on electrical performance and gate leakage, an initial compressive layer of SiN performs better than an initial tensile layer for the stress-memorization technique process. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3506399] All rights reserved.en_US
dc.identifier.doi10.1149/1.3506399en_US
dc.identifier.issn1099-0062en_US
dc.identifier.journalELECTROCHEMICAL AND SOLID STATE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1149/1.3506399en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/26193
dc.identifier.wosnumberWOS:000284317600020
dc.language.isoen_USen_US
dc.titleImpact of Strain Layer on Gate Leakage and Interface-State for nMOSFETs Fabricated by Stress-Memorization Techniqueen_US
dc.typeArticleen_US

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